Complete Design-for-Manufacturing reference with minimum trace widths, via sizes, annular rings, solder mask rules, voltage clearances, and a pre-production checklist — organized by IPC Class 2 and Class 3 requirements.
Design for Manufacturing (DFM) bridges the gap between an electrical schematic that works in simulation and a physical PCB that can be reliably produced at scale. Violating even a single DFM rule can cause fabrication yields to plummet, assemblies to fail in reflow, or — worse — pass inspection only to fail in the field.
The rules below are derived from IPC-2221 (Generic Standard on Printed Board Design), IPC-6012 (Qualification and Performance Specification for Rigid PCBs), and real-world fabricator capabilities. They are split into IPC Class 2 (standard commercial electronics) and IPC Class 3 (high-reliability: medical, military, aerospace).
Use this page alongside our Trace Width Calculator, Impedance Calculator, and Via Current Calculator to validate your design before sending Gerber files.
Trace width determines current-carrying capacity and impedance. Trace spacing governs voltage withstand, crosstalk isolation, and etchability. Both are constrained by the fabricator's copper etching process.
| Parameter | IPC Class 2 | IPC Class 3 | Typical / Recommended |
|---|---|---|---|
| Minimum Trace Width | 5 mil (0.127 mm) | 4 mil (0.102 mm) | 6–8 mil |
| Minimum Trace Spacing | 5 mil (0.127 mm) | 4 mil (0.102 mm) | 6–8 mil |
| Trace-to-Edge Clearance | 10 mil (0.254 mm) | 10 mil (0.254 mm) | 15–20 mil |
| Trace-to-Pad Clearance | 5 mil | 4 mil | 6 mil |
| Trace Width Tolerance | ±1 mil | ±0.5 mil | ±1 mil |
Copper weight matters: These minimums assume 1 oz (35 µm) copper. For 2 oz copper, increase minimum trace width and spacing by roughly 1–2 mil due to additional etching undercut. Check with your fabricator for exact capabilities.
Vias connect copper layers through drilled and plated holes. The annular ring — the copper ring surrounding the hole — must survive drill wander, registration tolerances, and plating thickness variations without breaking the electrical connection.
| Parameter | IPC Class 2 | IPC Class 3 | Typical / Recommended |
|---|---|---|---|
| Minimum Via Drill Size | 8 mil (0.2 mm) | 6 mil (0.15 mm) | 10–12 mil |
| Minimum Via Pad Diameter | 18 mil (0.457 mm) | 16 mil (0.406 mm) | 20–24 mil |
| Minimum Annular Ring | 5 mil (0.127 mm) | 4 mil (0.102 mm) | 5–6 mil |
| Via-to-Via Spacing | 8 mil | 6 mil | 10 mil |
| Via-to-Trace Spacing | 6 mil | 5 mil | 8 mil |
| Via Aspect Ratio (depth:diameter) | 8:1 | 10:1 | 6:1 |
| Microvia Drill (laser) | 4 mil (0.1 mm) | 3 mil (0.075 mm) | 4 mil |
Example: A 24 mil pad with a 12 mil drill produces a 6 mil annular ring — meeting IPC Class 2 with margin. If drill wander is ±3 mil, the worst-case annular ring is 3 mil, which still passes Class 2 minimum (5 mil minus 3 mil wander = 2 mil of margin).
Solder mask protects copper from oxidation and prevents solder bridges during assembly. Incorrect clearances cause mask-on-pad (cold joints) or missing mask dams (solder bridges between fine-pitch pads).
| Parameter | IPC Class 2 | IPC Class 3 | Typical / Recommended |
|---|---|---|---|
| Solder Mask Clearance (per side) | 3 mil (0.076 mm) | 2.5 mil (0.063 mm) | 3–4 mil |
| Minimum Solder Mask Web | 4 mil (0.1 mm) | 3 mil (0.076 mm) | 4–5 mil |
| Solder Mask-to-Board Edge | 0 mil | 0 mil | 5 mil |
| Minimum Solder Mask Opening | 8 mil | 6 mil | 8 mil |
Solder mask defined vs. non-solder mask defined (NSMD): For BGA pads, NSMD pads (where the mask opening is larger than the copper pad) are generally preferred because they increase the solderable area and improve joint reliability.
Silkscreen provides component reference designators, polarity marks, and assembly instructions. Ink printed over pads contaminates solder joints — always maintain clearance.
| Parameter | IPC Class 2 | IPC Class 3 | Typical / Recommended |
|---|---|---|---|
| Minimum Line Width | 5 mil (0.127 mm) | 4 mil (0.102 mm) | 6 mil |
| Minimum Text Height | 32 mil (0.8 mm) | 32 mil (0.8 mm) | 40–50 mil |
| Silkscreen-to-Pad Clearance | 6 mil | 5 mil | 8 mil |
| Silkscreen-to-Board Edge | 10 mil | 10 mil | 15 mil |
Ground and power planes form the backbone of signal integrity and EMI performance. Rules here ensure planes survive manufacturing and function correctly in the final product.
| Parameter | IPC Class 2 | IPC Class 3 | Typical / Recommended |
|---|---|---|---|
| Minimum Copper-to-Edge Clearance | 10 mil (0.254 mm) | 8 mil (0.2 mm) | 15 mil |
| Copper Pour-to-Trace Spacing | 8 mil | 6 mil | 10 mil |
| Thermal Relief Spoke Width | 8 mil | 8 mil | 10–12 mil |
| Minimum Copper Feature Size | 5 mil | 4 mil | 6 mil |
| Inner Layer Copper-to-Edge | 15 mil | 12 mil | 20 mil |
Drilling accounts for the largest share of PCB fabrication time and tooling wear. Correct drill sizing ensures plated holes pass connectivity tests and meet finished-hole tolerances.
| Parameter | IPC Class 2 | IPC Class 3 | Typical / Recommended |
|---|---|---|---|
| Minimum PTH Drill Size | 8 mil (0.2 mm) | 6 mil (0.15 mm) | 10 mil |
| Minimum NPTH Drill Size | 8 mil (0.2 mm) | 8 mil (0.2 mm) | 12 mil |
| Hole-to-Hole Spacing (PTH) | 10 mil | 8 mil | 12 mil |
| Hole-to-Copper Clearance | 8 mil | 6 mil | 10 mil |
| Hole-to-Board Edge | 10 mil | 10 mil | 15 mil |
| Drill Position Tolerance | ±3 mil | ±2 mil | ±3 mil |
Minimum conductor spacing increases with operating voltage. Internal layers benefit from the dielectric encapsulation of the laminate. External layers need wider spacing, especially without conformal coating. Values below are for sea-level altitude (< 3,050 m).
| DC or AC Peak Voltage | Internal Layers | External (Uncoated) | External (Conformal Coated) |
|---|---|---|---|
| 0–15 V | 2 mil | 2 mil | 2 mil |
| 16–30 V | 2 mil | 5 mil | 2 mil |
| 31–50 V | 4 mil | 10 mil | 4 mil |
| 51–100 V | 5 mil | 15 mil | 5 mil |
| 101–150 V | 8 mil | 20 mil | 8 mil |
| 151–170 V | 10 mil | 25 mil | 10 mil |
| 171–250 V | 15 mil | 30 mil | 15 mil |
| 251–300 V | 20 mil | 50 mil | 20 mil |
| 301–500 V | 30 mil | 80 mil | 30 mil |
Altitude de-rating: At altitudes above 3,050 m (10,000 ft), air insulation decreases. Multiply external clearances by 1.5× or more. Consult IPC-2221B Table 6-1 for exact de-rating factors. Pressurized equipment uses sea-level values.
Run through this checklist before submitting your design for manufacturing. Items marked Critical are the most common causes of fabrication rejects or assembly failures.
"I've seen hundreds of PCB designs rejected at the fab house for DFM violations that a 10-minute checklist review would have caught. The most common mistakes are annular rings that are too small, missing solder mask dams on fine-pitch QFPs, and forgetting to increase trace spacing for high-voltage nets. Build DFM checks into your design workflow — not as an afterthought before tapeout."
IPC Class 2 covers standard electronics (computers, telecom equipment, general industrial). Class 3 is for high-reliability products (medical life-support, military, aerospace). Class 3 has tighter tolerances — smaller annular rings, more precise drill placement, and stricter inspection criteria. Most commercial PCBs are manufactured to Class 2 standards.
Most standard PCB fabricators reliably produce 5 mil (0.127 mm) traces with 5 mil spacing. Advanced fabricators can go down to 3/3 mil, but this requires premium processes and costs significantly more. For the best balance of reliability and cost, design with 6 mil or wider traces wherever possible.
The annular ring is the copper ring around a drilled hole. If it is too small, drill wander during manufacturing can cause a breakout — where the hole touches or extends past the pad edge, breaking the electrical connection. A larger annular ring provides manufacturing margin and ensures reliable via connections across thousands of boards.
Via pad diameter = finished hole size + (2 × annular ring). For example, a 10 mil drill with a 5 mil annular ring needs a 20 mil pad. Always use the finished hole size (after plating), not the drill size. Plating typically reduces the hole by 2–3 mil per side, so plan accordingly.
Via-in-pad is often necessary for fine-pitch BGAs (≤ 0.8 mm pitch) because there is no room to fan out traces between pads. The vias must be filled with epoxy and capped with copper to create a flat surface for soldering. Unfilled via-in-pad can cause solder wicking, starving the joint of solder and creating reliability issues.
Voltage-dependent spacing is defined by IPC-2221. For example, 100 V requires 15 mil clearance on external uncoated layers but only 5 mil on internal layers (which are encapsulated in laminate). Conformal coating reduces external clearance requirements. Always verify with your specific safety standard (UL, IEC 60950, IEC 62368).
Acid traps are acute-angle copper features (typically less than 90°) where etchant pools during manufacturing. The pooling over-etches the copper, thinning or breaking the trace. Avoid routing traces at sharp angles — use 45° bends or arcs instead. Most modern EDA design rule checks flag acid traps automatically.
Export Gerber RS-274X (or Gerber X2) files for every copper layer, solder mask layer, silkscreen layer, and paste layer. Export drill files in Excellon format with separate files for plated and non-plated holes. Include a fabrication drawing with your stackup, material requirements, and special instructions. Use our Gerber Viewer to visually verify files before submission.
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