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Decoupling Capacitor Calculator
Select optimal bypass capacitors for stable power delivery to ICs.
mA
MHz
V
mV
Decoupling Strategy
Effective decoupling uses multiple capacitors to cover a wide frequency range:
- 100pFHigh frequency (>100MHz)
- 100nFPrimary decoupling (1-100MHz)
- 1-10µFLow frequency & transients
- 10-100µFBulk storage & high current
Minimum Capacitance Required
125.00 nF
Recommended Capacitors:
100pFC0G/NP0 ceramic
High-frequency noise (>100MHz)
Placement: Closest to power pins
100nFX7R ceramic
Primary decoupling (16MHz range)
Placement: < 5mm from power pins
10µFX5R/X7R ceramic
Bulk decoupling & transient current
Placement: Near IC, within 10mm
Current Draw
100.0 mA
Target Ripple
50.0 mV
PCB Layout Tips
Placement Priority
- Smallest caps closest to IC pins
- Place on same layer as IC
- Minimize via inductance
- Bulk caps near power entry
Common Mistakes
- • Long traces add inductance
- • Vias between cap and IC degrade performance
- • Using only bulk caps (no HF filtering)
- • Insufficient ground plane
Why Decoupling Matters
Digital ICs draw current in sharp pulses during clock transitions. Without proper decoupling, these current spikes cause voltage droops that can corrupt data, cause timing errors, or generate electromagnetic interference (EMI).
Voltage Stability
Capacitors act as local energy reservoirs, supplying instantaneous current that the power supply cannot deliver fast enough.
Noise Filtering
Creates a low-impedance path to ground for high-frequency noise, preventing it from coupling into sensitive circuits.
EMI Reduction
Reduces current loop area and contains high-frequency energy locally, minimizing radiated emissions.
Capacitor Types for Decoupling
| Type | Range | Frequency | Best For | Notes |
|---|---|---|---|---|
| C0G/NP0 | 1pF - 10nF | >100MHz | RF, high-speed digital | Stable, low loss |
| X7R | 1nF - 10µF | 1-100MHz | General purpose | Good balance |
| X5R | 100nF - 100µF | 100kHz-10MHz | Bulk decoupling | Higher capacitance |
| Tantalum | 1µF - 1000µF | <1MHz | Bulk storage | Watch polarity! |
| Electrolytic | 10µF - 10000µF | <100kHz | Input filtering | High ESR, polarized |
Best Practices
Do
- ✓Use multiple cap values in parallel
- ✓Place small caps closest to IC pins
- ✓Keep traces short and wide
- ✓Use solid ground plane under caps
- ✓Add one 100nF per VCC pin minimum
Don't
- ✗Route caps through vias if avoidable
- ✗Share caps between multiple ICs
- ✗Use only bulk capacitance
- ✗Ignore capacitor voltage derating
- ✗Place caps far from power pins