Calculate differential impedance (Zdiff) for edge-coupled microstrip, edge-coupled stripline, and broadside-coupled stripline configurations. Essential for USB, HDMI, PCIe, Ethernet, and other high-speed serial interfaces.
| Interface | Zdiff | Tolerance | Data Rate |
|---|---|---|---|
| USB 2.0 | 90 Ω | ±10% | 480 Mbps |
| USB 3.2 Gen 1 | 90 Ω | ±10% | 5 Gbps |
| USB4 / Thunderbolt | 85 Ω | ±10% | 40 Gbps |
| HDMI 2.1 | 100 Ω | ±10% | 48 Gbps |
| Ethernet (1GbE) | 100 Ω | ±10% | 1 Gbps |
| PCIe Gen 4/5 | 85 Ω | ±10% | 16/32 GT/s |
| DDR5 | 80 Ω | ±10% | 6.4 GT/s |
| SATA III | 100 Ω | ±10% | 6 Gbps |
| DisplayPort 2.0 | 100 Ω | ±10% | 80 Gbps |
| LVDS | 100 Ω | ±10% | 655 Mbps |
Differential pair impedance (Zdiff) is the impedance experienced by a differential signal as it propagates along two coupled transmission lines on a PCB. Unlike single-ended impedance where a signal is referenced to a ground plane, differential signaling uses two complementary signals (D+ and D-) that are equal in magnitude but opposite in polarity.
When two traces run in close proximity, their electromagnetic fields interact, creating mutual coupling. This coupling modifies the effective impedance each trace presents to the signal. The result is two distinct propagation modes:
When the two traces carry signals that are equal in amplitude but opposite in phase (the normal differential operating mode), each trace sees the odd-mode impedance (Zodd). The differential impedance is Zdiff = 2 × Zodd. Because the electric fields between the traces partially cancel, Zodd is lower than the uncoupled Z0.
When both traces carry signals in phase (common-mode noise, for example), each trace sees the even-mode impedance (Zeven). The common-mode impedance is Zcommon = Zeven / 2. Because the fields reinforce each other, Zeven is higher than the uncoupled Z0.
The mathematical relationship is straightforward: as you bring the traces closer together, coupling increases, Zodd decreases, and Zdiff decreases. Conversely, wider spacing reduces coupling, and Zdiff approaches 2 × Z0 (twice the single-ended impedance). This relationship is the key to designing differential pairs that hit your target impedance.
This calculator uses established analytical formulas from IPC-2141 and Wadell's Transmission Line Design Handbook to compute differential impedance. The computation follows a two-step process:
First, the uncoupled characteristic impedance of each individual trace is calculated using the IPC-2141 microstrip or stripline equations. This accounts for trace width (W), copper thickness (T), dielectric height (H), and the material's dielectric constant (Er).
The coupling factor between the two traces is computed based on the spacing-to-height ratio (S/H). Wadell's equations apply an exponential correction factor to derive Zodd and Zeven from Z0, then Zdiff = 2 × Zodd.
Where S = trace spacing (edge-to-edge), H = dielectric height
Where b = total dielectric thickness (2H + T)
The most common differential pair configuration. Both traces sit on an outer layer of the PCB with a ground plane beneath. This offers the easiest impedance control because both traces are manufactured simultaneously on the same layer, sharing identical copper thickness and etching conditions.
Both traces are on the same inner layer, sandwiched between two ground planes. The dielectric completely surrounds the traces, providing excellent shielding and consistent impedance. This is the preferred configuration for high-speed serial links routed through inner layers.
The two traces are on different layers, vertically aligned above each other. This provides very tight coupling and is used in specialized applications where routing density requires differential pairs to span multiple layers.
USB 2.0 requires 90 Ω differential impedance with ±10% tolerance. Route D+ and D- as tightly coupled pairs on the same layer. USB 3.x adds SuperSpeed pairs (TX and RX) that also need 90 Ω differential. USB4 and Thunderbolt move to 85 Ω. Maximum trace length for USB 2.0 high-speed is about 5 inches without equalization.
Typical stackup: 5 mil trace, 5 mil space, 4 mil dielectric on FR-4
HDMI specifies 100 Ω differential impedance. HDMI 2.1 supports up to 48 Gbps across four TMDS lanes. Keep trace lengths under 4 inches for HDMI 2.1 on FR-4. Use low-loss dielectrics (Megtron 6, Rogers) for longer runs. AC coupling capacitors should be 100 nF placed within 500 mil of the transmitter.
Typical stackup: 4 mil trace, 6 mil space, 3.5 mil dielectric on low-loss FR-4
PCI Express requires 85 Ω differential impedance. Gen 4 (16 GT/s) and Gen 5 (32 GT/s) demand careful impedance control and low-loss materials for traces longer than 8 inches. Route on inner stripline layers to minimize EMI. PCIe Gen 6 (64 GT/s) uses PAM4 encoding and requires even tighter impedance tolerance.
Typical stackup: 4.5 mil trace, 5 mil space, 3.7 mil dielectric on Megtron 6
Ethernet uses 100 Ω differential impedance. For 10GBASE-KR and 25GBASE-KR backplane Ethernet, insertion loss budgets are tight, so low-loss dielectrics and smooth copper (RTF or VLP) are essential. Place magnetics (Bob Smith termination) close to the PHY. Maintain pair-to-pair skew under 10 ps for multi-lane Ethernet.
Typical stackup: 5 mil trace, 7 mil space, 4 mil dielectric on standard FR-4 (1GbE)
Differential pair impedance (Zdiff) is the impedance seen by a differential signal traveling on two coupled transmission lines. It equals twice the odd-mode impedance (Zdiff = 2 × Zodd). For loosely coupled pairs, Zdiff approaches 2 × Z0 (twice the single-ended impedance).
Edge-coupled differential pairs have both traces on the same PCB layer with a horizontal gap between them. Broadside-coupled pairs place the two traces on different layers, vertically aligned. Edge-coupled is more common because both traces share the same manufacturing tolerances, making impedance control easier.
USB 2.0 and USB 3.x require 90 Ω differential impedance with ±10% tolerance. USB4 and Thunderbolt require 85 Ω ±10%. Maintaining these targets requires careful control of trace width, spacing, and dielectric thickness during PCB fabrication.
Reducing trace spacing (S) increases coupling between the traces, which decreases odd-mode impedance and thus lowers differential impedance. Increasing spacing reduces coupling, and Zdiff approaches 2 × Z0. For most designs, a spacing of 2-3 times the trace width provides a good balance between impedance control and routing flexibility.
Z0 is the single-ended (uncoupled) impedance. Zodd is the odd-mode impedance when differential signals propagate. Zeven is the even-mode impedance when common-mode signals propagate. Zdiff = 2 × Zodd, and Zcommon = Zeven / 2. As coupling decreases, Zodd and Zeven both approach Z0.
Online calculators use simplified analytical formulas that are good approximations. PCB manufacturers use 2D field solvers (like Polar Instruments Si8000) that account for trapezoidal etch profiles, solder mask, surface roughness, and other real-world effects. Expect 5-10% difference between analytical calculators and field solver results. Always confirm final dimensions with your manufacturer.
Use microstrip (outer layer) when you need lower loss, easier connector breakout, or are routing moderate-speed signals like USB 2.0. Use stripline (inner layer) for high-speed signals above 10 Gbps, when EMI is a concern, or when routing through dense areas of the board. Many designs use microstrip for connector breakout and transition to stripline for the longer routing segments.