Create a nominal symmetric layer stack and get first-pass controlled-impedance width hints.
Differential pairs use S = W; all values are first-pass estimates.
| Structure | Target | Width |
|---|---|---|
| Microstrip | 50 Ω single-ended | 35.37 mil (0.898 mm) |
| Stripline | 50 Ω single-ended | 12.51 mil (0.318 mm) |
| Microstrip | 90 Ω differential | 37.12 mil (0.943 mm) |
| Microstrip | 100 Ω differential | 28.10 mil (0.714 mm) |
| Stripline | 90 Ω differential | 10.66 mil (0.271 mm) |
| Stripline | 100 Ω differential | 6.43 mil (0.163 mm) |
Planning estimate: actual prepreg/core choices, finished copper, Dk, etch geometry, and impedance must be confirmed with the PCB manufacturer or a field solver.
The nominal remaining dielectric thickness is distributed evenly between copper layers, with core and prepreg labels mirrored around the board center. This is a planning model, not a fabrication-ready material schedule.